HW-V5-ML561-UNI-G【PDF 19/140 页】EVALUATION PLATFORM VIRTEX-5

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Memories

Table 3-1 lists the types of memories that the ML561 board supports.

Hardware Overview

Table 3-1:

Summary of ML561 Memory Interfaces

Memory Type

DDR400 SDRAM

DDR2 DIMM

DDR2 SDRAM

QDRII SRAM

RLDRAM II

Maximum Speed

200 MHz

333 MHz

333 MHz

300 MHz

300 MHz

Data Rate

400 Mbps

667 Mbps

667 Mbps

1.2 Gbps

600 Mbps

Data Width

32

144

32

72

36

I/O Standard

SSTL2

SSTL18

SSTL18

HSTL18

HSTL18

Data/Strobe

Ratios

8:1

8:1

8:1

18:1, 36:1

9:1, 18:1

When a larger data/strobe ratio is implemented, for example, a x36 QDRII device, the

smaller configurations can also be demonstrated by programming the FPGA for a smaller

data width, such as a 9:1 data/strobe ratio for the QDRII device.

DDR400 SDRAM Components

The Virtex-5 FPGA ML561 Development Board has two 200 MHz Micron

MT46V32M16BN-5B (16-bit) DDR400 SDRAM components that provide a 32-bit interface.

Each 16-bit device is packaged in a 60-ball FBGA package, with a common address and

control bus and separate clocks and DQS/DQ signals.

DDR2 DIMM

The Virtex-5 FPGA ML561 Development Board contains five PC-5300 240-pin DIMM

sockets for a maximum data width of 144 bits or a maximum depth of four DIMMs. The

sockets are arranged in a row leading away from the FPGA so they can share common

address and control signals. DIMM1 through DIMM4 share DQ/DQS signals to form a

deep 72-bit memory interface, while DIMM5 has separate DQ/DQS signals.

For the deep DDR2 interface, the sockets are to be populated starting at socket DIMM4.

Table 3-2 illustrates how the sockets should be populated based on the interface wanted.

Table 3-2:

Populating DDR2 DIMM Sockets

DIMM Interface

One Deep

Two Deep

Three Deep

Four Deep

Two Wide

DIMM Sockets

Populated

5 or 4

4 and 3

4, 3, and 2

4, 3, 2, and 1

5 and 4

Interface Width

72-bit

72-bit

72-bit

72-bit

144-bit

Populating the DIMMs in this order is necessary due to the placement of the termination

on the signals being shared. More detail on termination is given in “Board Design

Considerations,” page 36 .

Virtex-5 FPGA ML561 User Guide

UG199 (v1.2.1) June 15, 2009

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